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golang/arch

[mirror] architecture code

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Branches

release-branch.go1.15

release-branch.go1.14

release-branch.go1.13

Releases

Commits

arm64/instgen: support register with index in SVE This CL generates CL 759780. Change-Id: I430b74f92be3e6c5dc9c0f57fc8081612f16f874 Reviewed-on: https://go-review.googlesource.com/c/arch/+/759800 Re

arm64/instgen: add GP and SIMD register support for SVE This CL adds SVE instructions with GP and SIMD registers. This CL generates CL 759261. This CL also fixes the arm64 objdump test failure, it l

riscv64: add support for zbc instructions Add support for the disassembly of Zbc instructions and test cases. Change-Id: Icf1097ecdbbb68837836d1e9e79e8a4dd61d41bb GitHub-Last-Rev: 77c297cff58a74ad14

Issues

arch/x86: Fixed FCLEX/FNCLEX, FCMOVcc, etc... instructions not parse

x86spec: fix header parsing

x86: allow decoding of AVX instructions